Path search circuit

ABSTRACT

Scanning and path search circuits are provided in a switching exchange involving time division multiplex data and more particularly in an exchange employing pulse code modulation.

United States Patent [72] inventors Jacques Georges Dupleuxlssy-les-Moulineaux; Bernard Pierre Jean Durteste, Sevres; FrancisEmmanual Jean Robert, Boulogne- Blllancourt, France; Jean-Pierre LeCorre, deceased, late of Sainte-Genevieve-des-Bois, France by YvetteMarie Laurence Le Corre, administrator, Sainte-Genevievedes-Bois, France211 Appl. No. 22,105

[22] Filed Mar. 5, 1970 [4S] Patented Sept. 28, 1971 [73] AssigneeInternational Standard Electric Corporation New York, N.Y.

[32] Priority Mar. 6, 1969 33] France [54] PATH SEARCH CIRCUIT 6 Claims,28 Drawing Figs.

(52] US. Cl IMO/172.5,

Primary ExaminerGareth D. Shaw Attorneys-C. Cornell Remsen, .lr., WalterJ. Baum, Percy P, Lantzy, .1. Warren Whitesel, Delbert P. Warner andJames B. Raden ABSTRACT: Scanning and path search circuits are providedin a switching exchange involving time division multiplex data and moreparticularly in an exchange employing pulse code modulation.

imcsl SHEET 5 [IF 7 Eo 2. Fi 11 2 Y H 3 u 4 1 0 m M F9 2 3.1V 0 \9 c m.2 1 P R 0a a. .W 15 n 9 W A R M7 8 1 6.. fl O P D. E 4| R .m. M. 8 7 1 9M 2 6 9 n H G 13 3 A H 31. FD 6 7 .l I C 2 I .QOA w 5 6 I I L 4 2 9 d c1 5 QC R 110 D g 2 11 R d P .l m C m H a 4 lu 4 4 u r an u s s 9 c WC 1C 1 m u m 0 5w 1 L 1 Aw C PATH SEARCH cutcurr The present inventionconcerns scanning and path search circuits in a time multiplex dataswitching exchange, and more particularly in an exchange of this typeoperating in pulse code modulation.

In the case J. G. DUPIEUX et al. S-l-l3-I US. Pat. application Ser. No.7,477 filed Feb. 2, I970 for Time Multiplex Switching Center, a dataswitching exchange has been described in which the telephone operationssuch as detection of new calls, the reception of the dialling digits andits interpretation, the search of a free path in the switching networkbetween an incoming channel and an outgoing channel were carried out bya data processing machine.

It is however understood that for reasons of time and of cost, it may beinteresting to discharge the data processing machine of a certain numberof functions.

The object of the present invention is thus to make provision forcircuits carrying out certain scanning operations and certain search andpath identification operations.

In a time multiplex data switching exchange operating in pulse codemodulation in which the operations are controlled by a data processingmachine, the said switching exchange comprising a switching network,circuits of group of p-trunks or junctions or highways, if p is thenumber of digits of each channel message, connected to the inputs of theswitching network and provided for carrying out, on reception, a seriesparallel conversion and, on the transmission, the parallel seriesconversion of digits of the messages of channels of the ptrunks,detection and interpretation circuits of signalling digits associated toeach circuit of group of p-trunks comprising mainly a signalling memoryin which are stored for each channel of the group the expectedsignalling state and the indication of change or nonchange of thesignalling state with respect to the expected signalling state, junctordata memories connected to the outputs of the switching network, eachjunctor comprising, in addition to a data memory, a time path memory andspace path memories provided for setting up a connection between twochannels, the said memories being updated by the data processing machinein relation with the communications in course, a clock circuit providedfor supplying cyclic signals, the scanning and path search circuitswhich are the object of the present invention comprise means for cyclicreading of the signalling memories and of the time and space pathmemories, means associated to each signalling memory enabling to detect,on the one hand, the new calls and, on the other hand, the changes ofstate of the signalling other that the new calls, means associated toeach p-junction group circuit enabling to detect the trunks which areout of service, means for receiving and for decoding information sent bythe data processing machine, means associated to space path memoriesenabling to compare the space codes read on a cyclic way in the saidmemory to the space code sent by the data processing machine, means forreceiving selectively the signals coming (a) from means associated tothe signalling memories corresponding to the same switch (b) fromp-junction group circuits connected to a same switch and (c) from thespace and time path memories corresponding to a same switch, means forprocessing the signals received selectively from the above associatedcircuits in relation with the information supplied by the dataprocessing machine, the said means supplying the information required bythe data processing machine.

The above-mentioned and other features and objects of this inventionwill become apparent by reference to the following description taken inconjunction with the accompanying drawings in which:

FIGS. 1.0 to 1 illustrate the symbols used in the following figures;

FIGS. 2.4 to 2.3 illustrate the diagrams of the clock signals;

FIG. 3 represents the block diagram of a switching central exchangeoperating in time multiplex and in pulse code modu- Iation;

FIG. 4 represents the diagram of interconnection between the two stagesas well as the organization of the space path memories;

FIG. 5 represents the circuits associated to each group of trunksenabling to know the new calls, or the changes of the signalling state,or the alarms, or even the free channels;

FIG. 6 represents the circuits associated to the space path memory of ajunctor, the said memories corresponding to the first switching stage;

FIG. 7 represents the circuits associated to the space path memories ofthe junctor, the said memories corresponding to the second switchingstage;

FIG. 8 represents the registers and their associated circuits whichenable to control the scanning and path search circuits;

FIG. 9 represents the selection logic circuit;

FIG. 10 represents the sequential circuit of control of the differentphases of the logical circuit of FIG. 9;

FIG. ll represents the assembly of conductors coming from the controlcomputer;

FIG. 12 represents a circuit for sending space codes when it is foreseento use two scanning and path search circuits;

FIG. 13 represents another circuit for sending space codes when it isforeseen to use two scanning and path search circuits.

FIGS. La to 1.] give the meaning of certain symbols used particularly inthe drawings of the present patent.

FIG. l.a illustrates a coincidence electronic gate called simple ANDcircuit, which supplies a positive signal on its output when its inputs,represented by arrows touching the circle, receive simultaneously apositive signal. If we call A and B the signals which are present oneach one of the two input terminals, this circuit achieves the logicalcondition noted A.B.

FIG. 1.!) illustrates a mixing electronic gate, called 0R circuit, whichsupplies a positive signal on its output when a positive signal isapplied at least on one of the input terminals represented by the arrowstouching the circle. If one calls C and D the signals which are presenton each one of the two input terminals, this circuit achieves thelogical condition noted C+D.

FIG. 1.0 illustrates a multiple AND circuit, is. comprising, in the caseof the example, four AND circuits one of the input terminals of which isconnected to each one of the conductors 91a and the second inputterminal of which is connected to a common conductor 91b.

An input of a AND circuit will be said to be activated or energized whena signal is applied on the said input and that the AND circuit isconductive if all its inputs are simultaneously activated.

FIG. l.d illustrates a multiple OR circuit which comprises in the caseof the example, four OR circuits having two inputs 91c and 91d and whichdelivers, over the four output terminals 9le, the same signals as thoseapplied over said input terminals.

FIG. I.e illustrates a bistable circuit or flip-flop" to which a controlsignal is applied on one of its inputs 92-1 or 92-0 in order to set itrespectively to the I state or to the 0 state. A voltage of the samepolarity as the control signals is present, either on the output 93-!when the flip-flop is in the I state, or on the output 93-0 when it isin the 0 state. If the flip-flop is referenced B1, the logical conditioncharacterizing the fact that it is in the I state will be written BI,the one characterizing the fact that it is in the 0 state will bewritten fir FIG. l.f illustrates a group of several conductors, five forthe example considered.

FIG. l.g illustrates a multiplexing of conductors so that, in the shownexample, l0 output conductors 94j are connected in parallel to the sameinput conductor 94h.

FIG. 1.): illustrates a flip-flop register. In the case of the figure;it comprises four flip-flops the I inputs of which are connected to theconductors of group 920 and the l outputs of which are connected to thegroup of the conductor 93a. The digit 0 located at one end of theregister means that this latter is reset or clear when a signal isapplied to the conductor 9lh.

FIG. l.i. illustrates a decoder circuit which, in the shown exampleconverts a four-digit binary code group applied over the group ofconductors 940 into a 1 out of 16 codes, so that a signal appears ononly one among the 16 conductors 94b for each one of the code groupsapplied to the input.

F IG. 1. illustrates a code comparator which delivers a signal over itsoutput terminal 95:: when the three-digit code groups applied over itsterminals 95b and 95c are identical.

in the course of the description, it will be used frequently thereference of a signal preceded by the letter C in order to designate thebinary code the decoding of which supplies the said signal. Thus CV1designates the code to which corresponds the signal Vl.

Last, it will be noted, that in the different figures enclosed to thedescription. the electronic gates (AND circuits, OR cir cuits) do notbear references. in fact, each one of these gates is identified withoutambiguity in the description by the logical equation describing thefunction it performs and by the number of the figure, the reference ofeach elementary signal applied to it being shown near the correspondinginput. Thus, the AND circuit of FIG. La would be defined as the logicalcircuit supplying a signal Wv for the logical condition A.B (FlG. La).

FIGS. 2.0 to 23 represent the diagrams of the clock signals of the PCMcentral exchange and the table 1 gives the definition of them.

In the course of the description cases will be mentioned; these casesare listed below and will be mentioned in the description by thelettered reference of the said list:

a. case M. J. Herry et al. 3-2

h. Case J. G. Dupieux et al. 5-1-1 3-1 c. Case B. P. J. Durteste et al.l-2-2.

A way of achievement of a time multiplex data switching central exchangeand more particularly a central exchange of this type operating in pulsecode modulation or PCM, has been described in the case (b).

This improved switching central exchange comprises (FIG. 3):

a switching network SW shown under a matrix form and comprising forexample h rows R and h columns C. Only the rows R1, R2 and the column CShave been shown on the figure and the corresponding cross-points havebeen referenced RICS and RZCS.

h circuits ofgroup ofjunctions G1 to Oh;

it junctors .H to jh;

a marker circuit MKR having access to all the junctors. The

marker circuit is in fact a data processing machine provided for settingup the communication between two channels ending at the centralexchange. Owing to the number of operations to be carried out forsetting up the communications simultaneously, it is usually provided toassociate peripheral units to the data processing machine, the saidperipheral units carrying out certain operations; the same goes for thescanning and path search circuits which are the object of the presentinvention. In the continuation of the present description and in theclaims, the expressions of marker circuits. of data processing machineor even of computer will be used indifferently.

a clock unit CU which supplies the signals defined in table 1 and theFIGS. 2.0 to 2.g.

Each junctions group circuit such as G1 comprises:

a receiving circuit R1 of the messages received over p=8 incoming lines;

a synchronization circuit SCRl;

a group data memory MDGI comprising g=p m=l92 lines; this memory isselected on a cyclic way under the control of the signals IS;

a demultiplexing circuit DXGI from the switch SW;

a transmission circuit El of the messages to which are connected p=8outgoing lines;

Each junctor such as J5 comprises mainly a certain number of memories ofgf2=96 lines. which are:

a speech memory MDJ;

of the messages coming TABLE l.(IIA RAPTEIHSTIFS ill OF THE CLOCK THE PFSYSTEM ANI) SltiNALS iEXlllANliE TIME) BASIC "8) Unit Cycle duradura-Symbol tion tion Flgtirn TR S. Duration olthe repetition 2.n

period or frame (sum pling frequency: ti Ire). M Numher olehnnnvls in ajunction (in =24). VTJ VQ 245.2;15 125;;5 Channel time slot... .Lu 1Number oldiglts ofa message and num her of junctions in a group p=B).650 ns. 5.2 n Digit time slot v 2.1)

l,3flf)n 125m llilSi time slot 21 Hall basitime slot Set of as basetime-slot miles.

Set. ofg=1i2 hall base.

time slot codes.

650 its. [125 s.

teL. 650m. Synchronous time slots... 2.11 in V 650 ns. Asynchronous timeslots. '.Z.e is] 1896... 1560 ns. 1 s. ilnti-rlaeeil sets of signals Li[Al tAEJG 650 ns. 125 5 its and til. it, h, e, d 1625 ns. 650 ns. Finetime slot signals...... 2.! a], a2 ((11. d2] 281 us. 1625 ns. Ultra-tinetime slot signals dividing a signal (d) Eu into 2 equal time slots. Ct.tS Cyclical selection at sgnchronous time slots t Ct. tA Cyclicalselection at asynchronous time slots tA.

a time path memory MCT;

a synchronous space path memory MSS;

an asynchronous space path memory MSA;

The switching network of FIG. 3 is provided in order to establishconnections between it groups of junctions G1 to Oh comprising each oneg=l92 channels, each connection being set up through a junctor among h.Such a connection is constituted by two half-connections which connectrespectively to the junctor the incoming channel and the outgoingchannel; one of these half-connections being set up at a synchronoustime slot IS and the other one at an asynchronous time slot IA the ordernumbers of which being generally different. A connection necessitatesthe carrying out of a time switching in the junctor and of two spaceswitchings (one per half-connection) in the switching network SW.

The time switch is constituted by the combination in a junctor of aspeech memory MD! and of a time path memory MCT. The addressing of thespeech memory is carried out in a cyclic way under the control of thesignals :8 and in an acyclic way at the time IA under the control of theaddress code supplied by the time path memory MCT the selection of whichis also cyclic.

The space switch is constituted by the switch SW with electroniccross-points controlled either by synchronous space path memories MSSwhen it is required to set up a synchronous half-connection, or byasynchronous space path memories MSA when it is required to set up anasynchronous half-connection. Such a switch enables to carry out theconnection between groups of difierent junctions such as GI and G2.

The time and space switching will be quickly described for a connectionbetween the channel 1 of the group Gl (half-connection Gl:rSx) and thechannel y of the group G2 (half-connection G2zrAy), this connectionusing the junctor 15 (abbreviation of the connection Gl:lSx/J$/G2:!Ay).

The marker circuit MKR allocates to this connection to this connectionthe line A: of the junctor J5 and writes on the line y of the memory MCTthe code Cx defining the address 1 of the memory MD]. The marker circuitwrites also in the line x of the synchronous space path memory MSS thecode C(RlCS) permitting the selection in the switch SW of thecross-point RICS. It writes also in the line y of the asynchronous spacepath memory MSA the code (:(RZCS) permitting the selection in the switchSw of the cross-point RZCS.

At the time slot :Sx, the information contained in the lines x of thememories MDJ, MDG! and M88 permits the setting up of the half-connectionGlztSx. This latter is made by a transfer in both directions of databetween the junctor J5 and the group G1, vizus, first the transfer ofinformation contained in the line it of the memory MDJ towards thedemultiplexing circuit DXGI, afterwards the transfer of the contents ofthe line 1 of the memory MDGl in the line x of the memory MD]. It willbe observed that two messages are written in each line of the memoryMDGI, one of the messages is transferred during the synchronous timeslot tSx (synchronous half-connection) and the other one is transferredduring the asynchronous time slot rAx (asynchronous half-connection).

At the time slot tSy, the line y of the memory MCT is selected again andthe code Cx which is read controls again the selection at the time slottAy of the line x of the memory MD]; the line y of the memory MSA isalso selected at the time slot tSy and the code C( RZCS) permits theclosing at the time tAy of the cross-point R2C5 used for thehalf-connection G2:!Ay. This latter consists first in a transfer of thecontents of the line x of the memory MD] in the multiplexing circuitDXGZ then in a transfer of a message of the line y of the memory MDGZ inthe line it of the memory MDJ.

It is therefore seen that the time switch enables to match the timeposition of the incoming and of the outgoing channels by delaying theinformation received from G1 from the time slot rSx to the time slot lAyand by delaying the one received from G2 from the time slot tAy to thetime slot lAx.

As it has been mentioned with relation to FIG. 4, the group data memoryMDG is read in a cyclic way at gl2=96 synchronous time slots. But, thismemory receives 3 messages per cycle TR, so that each reading mustenable to read two messages. This group data memory is organized in sucha way as at each reading one has staticized on the output registers RG]and RGP (FIG. 5) two messages corresponding the one to a channel of oneodd junction (register ROI) and the other one to the homologous channelof an even junction (register RGP). The message of a channel of an oddjunction is processed during a synchronous time slot :8 whereas themessage of a channel of an even junction is processed during anasynchronous time slot 1A.

The switching circuit of FIG. 3 comprises a switching network SW with asingle stage. FIG. 4 represents a switching circuit which comprises aswitching network with two stages Q and 0', each stage having forinstance switches with 15 inlets and 15 outlets. The outlets orverticals L of the first stage 0' are connected to the inlets orhorizontals E of the second stage 0 in such a way as each switch of onestage may have access to all the switches of the other stage. The inletsor horizontals E of the stage Q are connected to the equipments of groupG and the assembly of the group equipments which are connected to thesame switch Q will be called supergroup S0. The outlets or verticals Lof the stage 0 are connected to the junctors J and the assembly of thejunctors which are connected to a same switch 0 will be calledsuperjunctor SJ. In the continuation of the present description, aconnection such as L'lEl will be called link.

A synchronous space path memory and an asynchronous space path memoryare associated to each vertical of a switch. These memories, in the sameway as the memories M88 and MSA of FIG. 3, comprise each one 312 lineswhich are selected on a cyclic way by the synchronous time slot signalsis; the code contained in a line it of a memory of a space path memoryidentifies the cross point of the vertical to which the said memory isassociated which will have to be closed at the time rSx or at the time1A: according to whether respectively a synchronous or an asynchronousmemory is involved. The fact that no cross-point is selected at the halfbase time slot Ix is shown by a particular code, for instance the code0000, the decoding of which does not correspond to any cross-point.

With such a switching network, we understand easily that the up of ahalf-connection requires the access to two space path memories, eithersynchronous or asynchronous, one associated to one vertical of a switchof the stage Q and the other one associated to one vertical of a switchof the stage 0. In order to simplify the access to these memories, theyare for instance grouped as shown on FIG. 4. This grouping has beendescribed in the case (b). Thus, the space path memories as' sociated tothe verticals U1 and L] of the switches Q'] and Q1 are grouped andassociated to the memories MCT and MD] of the junctor SJ 1-11. Thisgrouping is called horizontal grouping. In ajunctor, the synchronousspace path memories, associated to the stage Q and to the stage Q willbe respectively called M and M88, the asynchronous space path memoriesassociated to the stage 0 and to the stage 0 will be respectively calledMSA and MSA.

For a call, the first operation to be carried out by the centralexchange is the detection of this call; the following operation consistsin detecting the dialling digits which are transmitted by the changes ofstate (opened or closed) of the line of the calling subscriber; when thedialling number of the called sub scriber is known, the followingoperation consists in searching a free path in the central exchangebetween the calling subscriber and the called subscriber. If a free pathexists, it is set up as described in relation with FIG. 3. When theconversation is completed, the memories have to be updated and for thispurpose the path used from the incoming channel assigned to the calledsubscriber is to be known, this operation of search of the used path iscalled path identification.

The detection operations of a call, of path search and pathidentification as well as others, are carried out by the circuit objectof the present invention under the control of signals of nine programsreferenced P16 to P24, the said signals being supplied by the dataprocessing machine which supervises the whole of the circuits of thecentral exchange. The table 2 gives the meaning of the differentprograms. We shall notice that the programs P20 to P24 concern scanningswhereas the programs P16 to P19 concern a path search or a pathidentification. These programs are coded under the form of a four-digitcode which is, for instance, supplied by the data processing machinewhich controls the central exchange.

It will be also observed that the search of a free link L' and theidentification of a busy link L' are two identical operations carriedout under the control of a same signal of program, vizus the signal P16when each p-junction group circuit is connected to the two inlets of theswitching network or the signal P17 when each p-junction group circuitis connected to a single inlet of the switching network. This last modeof connection is the one of FIGS. 3 and 4 and, in this case, as it hasbeen mentioned previously, the message of a channel of an odd trunk isprocessed during a synchronous time slot :5 whereas the message of aneven trunk is processed during an asynchronous time slot M. In the firstmode of connection, which has been described in the case (b), each oneof the two messages read in a same line of the group memory may beprocessed selectively, at a synchronous time slot or at an asynchronoustime slot.

TABLE 2 Programs Meaning P16 Search of :1 Iron link L or ldantif cationof a busy link L' between a switch of the stage Q and a switch of thestage Q at a given synchronous or asynchronous timv t'x in the casewhere each p-junction group circuit slot is connected to two inlets ofthrswitching network.

P17 Search of a free link L or identification of a busy link L between aswitch of the stage Q and a switch of the stage Q at agiven time slott'x in the case Wllll'l' p-junction group is connected to n single inletof the switching network.

P18 Search of a free path between a free link at a time slot t'.\ andone of the allowed outgoing channels at our of tintime slots t'y.

Pl9 Identification of tho junctor and ol tlw time slot ty uswl forconnecting a link. used at the time t'x, in an outgoimz channel.

P20 Dvtoction of new calls.

., lh tnction of the dnsynchronizvil trunks.

. lh-tvction oi the highways in which 1h nltrrnnt Mark Inversion rule ofthe IHYSSQIZI' signals ha bw-n inlrimrwl.

P23 l)i-ti-ction of tho highways in which thv nvrrauh Illilh signals amno longer i-laboratetl. P24. Detection of the changu of state ofthisignnllinu signals.

The codes of programs as well as the other pieces of information whichare necessary are supplied by the data processing machine under the formof five lo-digit words which are recorded in the five registers R31 toRgS of the circuit of FIG. 8. The 16 digits of each word are transmittedby the group of conductors E02 (FIG. ll). The choice of one of the fiveregisters is obtained through the code one out of five staticized on theregister RRg the inlets of which are connected to the group of fiveconductors 501. This code for choosing one register is sent at asynchronous time slot but is only used at the following asynchronoustime slot during which the word of 16 digits is sent. During theasynchronous time slot, the computer sends also, over the group of fourconductors Be, the writing orders Y4 to Y7 of the parts of words of fourdigits each. In order not to overload FIG. 8, only the incoming circuitsof the register Rgl have been shown, but it is to be understood that theother registers have the same inlet circuitsv TABLE 3 Registers DigitsMeaning Ilgl. 1 to 4. Code of the supcrjunctor CSJ. to 8. Code of theSIEJBIQIOUP C80. 1! to 12 Space code C or CE. 13 to 1ti Program code.

Rg2 1 to 15. s Mask of the allowed groups, links or junetors. 16 V Thecircuit may or not call the computer at the end of a program.

Rgli and l to 16. Mask of the allowed outgoing channels.

Rg4. 17 to 24.

25 to 27. Allowed highway.

Not used. 29 to 32. Space code CL of the link.

Rgfi. l to s. Time code Ct written by the computer or time code of theresult. J to 1'1. Space code of the result.

iii to 16. State of the sequential.

Table 3 gives the meaning of the different groups of digits. The decodercircuit Dcl is associated to the four flip-flops 13 to 16 of theregister RgI and supplies one of the signals of program P16 to P24. Thestate signals of the four flip-flops 9 to 12 of the register Rgl areapplied, on the one hand, to the decoder circuit Dc2 which supplies oneof the signals E1 to E'lS corresponding to an inlet of a switch and, onthe other hand, to the comparator circuits C'p and Cp of FIGS. 6 and 7.The decoder circuit Dc3, associated to the four flip-flops 5 to 8 of theregister Rgl, supplies the signals of selection 5G! to SGIS of one ofthe supergroups. The decoder circuit D04 associated to the fourflip-flops 1 to 4 of the register R3 1 supplies the signals of selectionSJI to SJ of one of the superjunctors.

The state signals M1 to M15 of the flip-flops 1 to 15 of the registerR32 are used as a mask in order to forbid the choice of certain groups,links or junctors during the different programs. The signal of the l6thflip-flop of the register R32 is used for informing the circuit objectof the present invention that the data processing machine eitherrequests or not to be called as soon as a result has been obtained.

The registers R33 and R34 are grouped in one single register of 32flip-flops. The flip-flops 25 to 27 store the code of the allowedoutgoing junction for carrying out a connection and the flip-flops I to24 store the mask of the allowed outgoing channels in the said junction.This information is used during the program P18 the aim of which (table2) is to search a free path between a free link at the time slot I): andone of the allowed outgoing channels, each one of the outgoing channelscorresponding to a certain clock time t'y. It is thus understood that itis necessary, at each allowed time slot r Y, to determine if a free pathexists between the free link at the time slot (x and the allowedoutgoing channel. The different allowed time slots r'y are obtained bycomparison of the clock code C! formed by the eight digits Al to A8 tothe different codes of the allowed outgoing channels. To this effect,provision has been made for a first comparator Cpl (FIG. 8) receiving,on the one hand, the signals of the digits 25 to 27 of the registers3-Rg4 and on the other hand the signals A7 and A8 ofthe clock code Cr;provision has also been for a decoder D05 of the digits Al to A5 of thecode Cr. the code I out of 24 appearing over the 24 outputs of thedecoder DcS being compared to the code constituted by the digits I to 24of the registers RgS-Rg4. This comparison is carried out through amultiplicity of 24 AND circuits, an AND circuit per each channel, thetwo input of which are connected to the corresponding outputs at thesame channel of the registers Rg3Rg4 and of the decoder DcS. The outputsofthe circuits are connected to a same OR circuit the signal of whichmeans that there is identity. Thus. ifthe code ofmask is l I followed by22 zeros (channels and 2 allowed). there will be identity for the twoclock codes C! which supply after decoding the code constituted by thedigit I followed by zeros and to the code ()I followed by zeros. Theidentity signals supplied by the comparator circuits (pi and Cp2 areapplied loan ANI) circuit the output signal of which means that theclock code Al to A8 corresponds to one of the allowed channels in adetermined trunk. In order to respect certain durations, this identitysignal ID is delayed by one digit time slot through a flip-flop set tothe I state at the ultrafine time slot d2 and set to the 0 state at thefine time slot c; the delayed signal will be referenced ID'r.

The flip-flops 29 to 32 of the registers Rg3-Rg4 staticize the code CL'of the link which must be used for connecting a junctor to an outgoingchannel (program P18). The decoder circuit D06 associated to theseflip-flops supplies the selection signals L! to LlS.

The flip-flops I to 8 of the register RgS staticize the code of theincoming channel for which a free path is searched. The code iscompared, in a circuit Cp3. to the clock code Ct; when there isidentity, the comparator supplies a signal ID which is staticized at theultrafine time slot d2 in a flip-flop, the said flip-flop being reset atthe ultrafine time slot c; in this way, the signal ID, in the same wayas the signal ID, is delayed for being used at the following time slot:it is then referenced IDr. When each one of the group circuits G isconnected to only an inlet E of a switch (FIG. 4), the eight digits ofeach code must be compared. However, it has been described in the case(b) a different organization which consists in connecting each groupcircuit to two inlets E of a same switch. Such an organization allowsthat each one of the two messages read in a same line of the group datamemory to be transferred, selectively, at a synchronous time slot or atan asynchronous time slot. In order to take into account such anorganization, the comparison for the program P16, is limited to theseven most significant digits in such a way as the signals ID and [Drlast two digit time slots.

The flip-flops l to 8 of the register R35 are used also for receivingthe time code which results from the search supplied by the register R37of the circuit of FIG. 9.

The flip-flops 9 to 12 of the register R 5 are used for staticizing thespace code resulting from the search supplied by the register R39 of thecircuit of FIG. 9.

The flip-flops 13 to I6 of the register RgS are used for staticizing thecodes of the different phases of the sequential circuit; at the startingof a program, the data processing machine staticizes therein the code1,000, the other codes are staticized by means of signals supplied bythe sequential circuit PC ofFIG. I0.

In the case of scanning programs P20 to P24 and of the program P18, thesignals resulting from the decoding of the program code are applied tocircuits associated to different groups of trunks. FIG. 5 illustratesthese various circuits associated to a p-junction group which are: thedetection circuit ofthe new calls, the detection circuit of the changesof state of the signalling other than the new calls, the detectioncircuit of the trunks which are out of service, the detection circuit ofthe free channels corresponding to the trunks which are not out ofservice, this latter circuit being used during the program P18. Thesignals of the programs P20 to P24 as well as P18 are appliedsimultaneously to the whole of the group circuits of the centralexchange; however, during a program, only the signals coming from asupergroup SG which is identified by a fourdigit code supplied by thedata processing machine (register Rgl, FIG. 8) are used. The supergroupswill be called by the references G! to SG or even by the total referenceSGu.

In the case (c) circuits enabling to detect the changes of state of thesignalling signals of a p-junction group having each one m channels havebeen described. These circuits comprise mainly a memory (pXm )/2 linesin which the information contained in one line of memory enables toprocess the signalling of two channels of the group considered, vizus achannel of an odd trunk and a channel of an even trunk. In theparticular case described, each line of the signalling memory MST (FIG.5) comprises two seven-digit words references S1 to S7 for the oddtrunks and S'] to 8'7 for the even trunks. The digits S1 and S2 (or S']and S2) are reserved to the indication of the expected signalling state,for instance, the code 01 means that the expected state is the free"state; the digits S3 and S4 (or 5'3 and 8'4) are reserved to theindication of the change of state in the signalling received, forinstance the code 11 means that the signal received is different fromthe expected signal. The meaning of the three other digits S5 to S7 (orS'S to 5'7) will not be given since they play no role in the circuitobject of the present invention.

In the FIG. 5, we have only shown the flip-flops S1 to S4 and S'l to 5'4of the register RST in which are staticized at each synchronous timeslot the contents of one line of the signalling memories MST/I for theodd trunks and MST/P for the even trunks The new calls will be detectedby the condition (Sl+S2) 83.84 or [(Sl+S'2) S'3.S'4]. These logicalsignals appear at the beginning of each synchronous time slot S in allthe group circuits of the central exchange but are taken into accountonly in the case of simultaneous presence of the signal of the programP24 (change of state) or P (new calls), of the signal S in the case ofan odd trunk and of the signal tA in the case of an even trunk, of thesignal of selection 8614 of the supergroup, and of the signal of thefirst phase Pcl of the program.

In the case (a), the synchronizing circuits of the signals received overa p-junction group have been described. It has been seen that when thesynchronization code was not detected three times in succession over atrunk, the said trunk was considered as being desynchronized and asignal S; appeared at each digit time slot mn reserved to the processingof a channel of this trunk. In FIG. 5, the signal Sy means that one ofthe trunks of the group is desynchronized, the said trunk beingidentified by the digit time slot mn during which the signal S; appears.In the circuit object of the present invention, this signal S;constitutes one of the three alarm signals, the two other alarm signalsmeaning one, referenced RB (FIG. 5) that the Alternate Mark Inversion ofthe message signals has been infringed in one of the trunks identifiedby the digit time slot in course and the other one referenced PM (FIG.5) that the signal of the average phase of the signals received is notelaborated in one of the trunks identified by the digit time slot incourse. The Alternate Mark Inversion rule concerns a certain mode oftransmission of the message signals in which two successive digits l ofone message are transmitted under the form of two pulses of differentpolarity. The infringement of this rule is detected in the inputrepeater of the incoming trunk circuit. The signal of the average phasewhich is elaborated in each repeater of a PCM transmission line is usedfor reconstituting the message signals; its absence has as consequencethe impossibility of reconstituting the messages and it is foreseen toinform the data processing machine thereof.

During the program P18, it is necessary to know if the allowed outgoingchannels are free and correspond to trunks which are not out of service.As it will be seen during the explanation of the process of the programP18 the alarm information must be available during two successive digittime slots, the first digit time slot must be a synchronous time slotand the second digit time slot must be an asynchronous time slot. But,each trunk of a group is processed at the digit time slot mn associatedto this trunk, therefore the alarm signals coming from odd trunks canonly appear at the odd digit time slots mn, i.e. at the synchronoustimes 18 as shown on FIGS. 2.b and 2.11, and the alarm signals comingfrom the even trunks can only appear at the asynchronous time slots IA(FIGS. 2.1: and 2.e). It is understood that in order to store the alarmsignal during a synchronous time slot and during the followingasynchronous time slot, it is necessary to make provision forflip-flops. In the case of four odd trunks ofa group, one singleflip-flop is sufficient. On the contrary, in the case of the four eventrunks, the alarm signal appears only during the asynchronous part of abase time slot and it is thus necessary to make provision for oneflip-flop per even trunk.

In FIG. 5, the alarm ignal Drl of an odd trunk appears for the logicalcondition (Sy+RB+PM)tS.b and the alarm signal D0? of an even trunk suchas N2 appears for the condition (;-l-RB1rAPM)N -rA.h, the signal N2coming from the decoding of the digits A6 and A7 of the clock code C! bythe decoder circuit Dc9. The flip-flop corresponding to the odd trunksis reset at the beginning of each synchronous fine time slot rS.awhereas a flip-flop corresponding to an even trunk, such as N2 is onlyreset when the alarm signal disappears, i.e.

for the condition S+RB+PM (inverter circuit 15 of FIG. 5

The fact that one channel is free and available (lack of alarm) will bedetected by the condition D rI.S I.S2 for one channel of an odd trunkand by the condition WS'TS'Z in the case of an even trunk.

It has been seen, in relation with FIG. 3, that the code 0000 read inthe line .1: of the synchronous and asynchronous space path memoriesmeans that no cross-point at all of the corresponding vertical wasclosed at the time slot (S1: in the case of a synchronous memory or atthe time slot tAx in the case of an asynchronous memory. It isunderstood that in order to know if one vertical ofa switch is free itis sufficient to com pare the 3 space codes contained in the twosynchronous and asynchronous memories to the code 0000, the identitymeans then that the vertical is free at the time determined by the rankof the line read, the choice of the synchronous or asynchronous time isdetermined by the memory in which the code 0000 has been read.

Reversely, in order to know if one cross-point of one vertical is busy,it is sufficient to compare the space code of this cross-point to the 3space codes contained in the two synchronous and asynchronous space pathmemories associated to this vertical; the identity means that thiscrosspoint is used at the time determined, on the one hand, by the rankof the line read and, on the other hand, by the memory containing thesaid code.

FIG. 6 represents the memories M and MSA and their associated codecomparator circuit Cp. This figure shows that the memories are read in acyclic way at the synchronous time slots IS and that the two codes readat each time slot IS are transferred in the registers RSS' and RSA. Thecodes of the registers RSS' and RSA' are compared, respectively at thetime slots t8 and IA to the code CE sent by the computer through theflip-flops 9 to 12 of the register Rgl (FIG. 8 The result of thecomparison (signal id) is taken into account only in the presence of thesignal of selection 5611 of the supergroup and of the signal of thefirst phase Pcl of the sequential circuit.

The mode of search of a space path in the second stage 0 is identical tothe one of the first stage and the corresponding circuit is similar. Itcomprises, as shown on FIG. 7. a code comparator Cp which receives, onthe one hand, the code CE and on the other hand the space codes suppliedby the registers RSS and RSA and coming from memories M85 and MSA.Additional conditions are nevertheless foreseen over the identity signalid. In effect, in the FIGS. 3 and 4, it has been assumed, on the onehand, that all the inlets E were connected to group circuits and, on theother hand, that the whole of the central exchange was controlled by adata processing machine which was able to carry out all the necessaryoperations for the setting up of a telephone communication such as thereception of the dialling, the updating of the memories of the junctors,the detection of the new calls, the search or the identification of apath. The circuit object of the present invention is provided, as it hasbeen mentioned previously, for discharging the computer of the scanningoperations of new calls, the scanning of the changes other than the newcalls, the scanning of the alarms, the search and the identification ofpathv In order to discharge the computer of the operations of receptionof the dialling and the up-dating of the memories of the junctors,provision is made for circuits connected in the same way as the groupcircuits, to inlets E of the switching network which have thus access tothe memories of the junctors through the switching network. Suchcircuits have been mentioned in the case (b). With respect to thecircuit object of the present invention, these circuits, calledmultisignallers," are considered as group circuits so that the callscoming from these units can be detected or even a free path between amultisignaller and a subscriber can be searched, the said path beingthen stored in the memories of the junctors. Besides, for certainoperations carried out by these units at preset time slots rw, inparticular the operations of up-dating the memories of the junctors, thepath is not stored in the memories and the space codes of thecross-points are supplied directly by the said multisignaller at thetime slots tw. These space codes are also applied to the comparatorcircuits Cp and Cp (FIGS. 6 and 7) instead of the codes read at the timeslots tw in the memories. It is understood that half-connections whichexist in the central exchange are not all half-connections through whichpasses a conversation between two subscribers. Then, in order to knowthe type of half-connection, it is foreseen to store it. For thispurpose, the junctor memory comprises two additional columns 5 and A(FIG. 7) which indicate if the halfconnection is a conversation (signalCV) during a synchronous time slot (column S) or during an asynchronoustime slot (column A). The signal CV acts on the output signal id of thecomparator Cp. For the program P18, the signals of identity id and ofconversation CV cannot exist simultaneously because as soon as there isa conversation the space ggde is different from zero; then one hasalways the signal M1, the signal indicating a free junctor appears forthe condition id. CV.

In the program P19 provided for identifying, in a first step, thejunctor used at a time slot 1): in a conversation link and, in a secondstep, the time slot t'y of the outgoing channel used, the signal Mlappears it", on the one hand, there is identity and conversation(condition id.CV, FIG. 7) and if, on the other hand, the signal idappears at the time slot t'x (condition Pl9.D e. ID.SJ.v.Pcl, FIG. 7).This signal M1 is stored in an additional column of the data memory ofjunctors MD! in the line selected at this instant, the said lineselected being the line 1: it" the time slot t'x is synchronous or aline z the code Cz of which has been read at the synchronous time slotrSx in the time memory MCT if the time slot I): is asynchronous. If thetime slot r'x is synchronous, the line x of the memory MD] will be againselected at an asynchronous time slot rSy which is the searched timeslot. If the time slot I): is asynchronous, the line 1 of the memory MDJwill be again selected at the synchronous time slot tSz which is thesearched time slot.

It will be noticed that if the time slot !'x is asynchronous, thesynchronous time slot rSz is given directly by the code C: read at thesynchronous time slot t'x in the memory MCT.

The circuit of FIG. Sis associated to a group ofp-trunks and thecircuits of FIGS. 6 and 7 are associated to a junctor; the informationsignals which they supply are staticized in the register RG (FIG. 9) inwhat concerns the information coming from the circuit of FIG. 5 and inthe registers RM and RJ (FIG. 9) in what concerns the information comingrespectively from the circuits of FIGS. 6 and 7. Each register comprises15 flip-flops which enable to staticize the IS information coming from asupergroup or from a superjunctor. These three registers are cleared atthe line time slot c of each digit time slot and written at eachultrafine time d2 of the first phase Pcl of a program. The state signalsof these registers are applied to AND circuits controlled by the signalsof program, the identity signals lDr and IDr, the signals of selectionE! to E 15 of one of the groups, the signals of selection L'I to L'lS ofone of the links. The circuit of FIG. 9 enables to process theinformation contained in the registers RG, RM and R1 in order to obtaina clock code and a space code. Thus, in the case of a scanning programof new calls, this new call is identified by the time slot l'x duringwhich it is detected and by the space code of the group from it comes.

Each program comprises three phases which are elaborated through asequential circuit PC illustrated by FIG. 10. It comprises theflip-flops I3 to 16 of the register RgS of FIG. 8 in which the computerwrites the code 1000 at the beginning of each program. At the fine timeslot 0, the digits I3 and 14 are transferred in a register Rgl0associated to a decoder circuit D07 supplying the phase signals Pc0 toP03; table 4 gives the correspondence with the codes. The passage fromone phase to the following one is controlled by the signals VA and VGresulting from the state of the logical circuit of FIG. 9. Themodification of the digits l5 and 16 is obtained by signals resultingfrom the time conditions provided for limiting the time of each program;thus the signal De appears when certain clock codes are detected and thesignal Fi appears when the same clock code is detected provided thefirst signal De should have already appeared. These codes will bedefined in the course of the description of the operation mode of theprograms.

TABLE 4 Meaning Phases The operation mode of the various which issummarized in table 2 will be Program P20 The aim of this program is todetect the new calls. For this purpose the data processing machinesupplies the following information:

the code of the program P20,

the code ofthe supergroup SGu to which we are interested,

the code of the mask forbidding certain groups,

the code corresponding to the phase Pcl.

At each synchronous time slot, the IS information concerning the oddtrunks (FIG. 5) of the supergroup SGu are staticized in the register RG(FIG. 9), the IS information concerning the even trunks are staticizedat each asynchronous time slot. This information is transferred in theregister R36, previously cleared by the signal Pc3.b of the precedingprogram, through the series of AND circuits SE1 controlled by the signalP20, the series of OR circuits S01 and the series of AND circuits SE4controlled by the signal PcLb. The outputs of the registers R36 areconnected to the series of AND circuits SE5 the two other inputs ofwhich receive, on the one hand, the signals of mask M1 to M15 and, onthe other hand, the output signals of the register R38 all theflip-flops of which are in the I state by the signal PI8.Pcl.b. If atany time slot t'x a channel is calling in a group allowed by the mask,one of the AND circuits SE5 is opened and supplies a signal VA which,through the OR circuit 1, the inverting circuit 2 and the multiple ANDcircuit 10, prevents at the ultrafine time slot Pcldl the writing of theclock code Ct'x-l-l in the register Rg7; the clock code Ct'x which isstaticized identifies the calling channel in a group. In order todetermine the group or for selecting one of the possible groups if thereare several channels from one supergroup which are calling at the sametime slot I'x, it is provided a selection circuit comprising theregister Rg9; the

programs the meaning of now described.

decoder DcB of the four digits A to A8 of the clock codes, the ANDcircuits SE6 the two inputs of which are connected on the one hand tothe outputs of the AND circuits SE5 and on the other hand to the outputsHl to H of the decoder Dc8.

Through the AND circuit 11 (FIG. 10) controlled by the signal Pcl, theoutput signal VA of the OR circuit 1 (FIG. 9) elaborates the passagesignal to the phase P02 (FIG. 10) during which the one of the callinggroups is chosen. When one of the AND circuits SE6 opens, its positionand thus the group to which it corresponds are determined by the outputH of the decoder Dc8 which is energized at this instant; the code ofgroup is thus the code formed by the digits A5 to A8 of the clock codeC! at this moment; the said digits are transferred in the register Rg9at the ultrafine time slot Pc2.d1 through the multiple AND circuit 6controlled by the output signal VG of the OR circuit 5. The outputsignal VG of the OR circuit 5 controls also the shifting to the phasePc3 (condition VG.Pc2.d, FIG. 10). The results of this search of newcalls, vizus the identity of the channel (register Rg7) and of the group(register Rg9) are transferred respectively in the fli flops 1 to 8 and9 to 12 of the register RgS (condition W31 i, FIG. 9).

In the case where no channel at all is calling in an allowed group, itis foreseen to limit the duration of the search to less than twocomplete cycles. For this purpose, provision is made for elaborating asignal De when a certain clock code Ct'c, chosen beforehand, is detectedduring the phase Pcl (condition P+P24).C!'c,Pc1, FIG. 10), to elaboratethereafter a signal Fl where the code Cr'c appears a second time duringthe phase Pcl (condition (P20+P24).Ct'c.Pc1.De, FIG. 10), and to shiftto the final phase Pc3 if no calling channel has been detected(condition PcLFLW; FIG. 10).

Program P24 The aim of this program is to detect the changes of state ofthe signalling which do not correspond to new calls and is identical tothe program P20 described hereabove.

Programs P21, P22, P23

The aim of these programs is to detect whether a trunk of any of thesupergroup 86a is out of service and cannot therefore be used.

For this purpose, the data following information:

the code ofone of the programs P21, P22 or P23,

the code of the supergroup 80a to which we are interested,

the code of the mask forbidding certain groups,

the code corresponding to the phase Pcl,

the code of the trunk to which we are interested,

the code of the mask of the channels constituted by the digits 1 only.

At each synchronous and asynchronous time slots, the alarm informationcorresponding to one of the three programs are written in the registerRG; they are transferred in the register Rg6 only when the presence ofthe identity signal lD'r is applied to the AND circuits SE2. In thismanner, only the alarm signal corresponding to the trunk specified inthe programs is taken into account.

The processing of the information is then identical to the one describedin relation with the program P20. Then, the signal VA appears if thetrunk is in alarm in any one of the groups and the code of this trunk isgiven by the digits A6, A7 and A8 of the clock code staticized in theregister R37, the code of the group is the one contained in the registerRg9.

At the beginning of a program, the clock code is any one and inparticular the three less significant digits A6, A7 and A8 which givethe code of trunk do not correspond in general to the trunk to which weare interested. Then, it is necessary to provide for a search time whichenables to scan at least once all the trunks. The signal De appears thenwhen a certain code Ctj formed by the digit A6 to A8 of the clock codeis detected a first time and the signal Fr appears for the secondoccurrence of this code Ctj.

Program P16 The aim of this program is to search a free link or toidentify a busy link between a switch Qu and a switch of the secondprocessing machine supplies the stage 0 at a given time slot t'xsynchronous or asynchronous in the case where each circuit of group isconnected to two inlets ofa switch. The data processing machine suppliesthe following information:

the code of the program P16,

the code of the switch Qu, i.e. in fact the code of the supergroup SGu;owing to the grouping of the memories (FIG. 4), the memories M and MSAare in the superjunctor $114,

the time code Clx limited by the signal P l6 (FIG. 9), to the seven mostsignificant digits since the inlet E of the switch Qu may be usedselectively in synchronous or asynchronous time slot if it is assumedthat each group is connected to two inlets of a switch,

the code of mask of the links,

the code of the phase Pcl of the sequential circuit,

the code 0000 for a search (or the code CE of the inlet E for anidentification) in the flip-flops 5 to 8 of the register Rgl.

At each synchronous time slot, the code 0000 (or CE) is compared to thespace code read at this time slot in the memory M58 and, at eachasynchronous time slot, the said code is compared to the space code readat the preceding synchronous time slot in the memory MSA (FIG. 6). Theresults of these comparisons corresponding to the memories M88 and MSAassociated to the switch Qu are transferred in the register RM (FIG. 9);they are taken into account only during the presence of the signal lDr(AND circuits SE7), the said signal having a duration of a base timeslot since only the seven most significant digits of the code Cr'x andof the clock code Ct are compared.

At the output of the AND circuits SE7, the information follows the sameprocessing as during the program P20; thus, if one of the links allowedby the mask is free (or identified), the signal VA appears and the codedisplayed by the register R37 (FIG. 9) gives the code of the channel inthe group, i.e. the synchronous and asynchronous time slot; the code ofthe free link L (or identified) is given by the register Rg9.

The processing time of the information in the case where there is noresult is limited to the duration of the signal lDr in this particularcase, i.e. a base time slot. The signal De appears for the condition(P16+Pl7).lDr.Pcl, (FIG. 10) and the signal Fi for the condition(Pl6-i-P17).De.tA.Pc1, (FIG. 10). Program P17 This program is identicalto the program P16, but is applied in the case where each group circuitis connected to one single input of the switch. The time code Ct'xcomprises then eight digits so that the signal IDr lasts only a digittime slot.

Program P18 The aim of this program is to search a free path between afree inlet E at a time slot rx ofa switch Qv and one of the outgoingchannels which are allowed and free of a trunk connected to an inlet E'wof a switch Qu. All the junctors, connected to the switch Qv, which arefree at the time slot rx are determined first then it is determined ifone of the allowed outgoing channels ofa trunk connected to the inletE'w, if the link L'uv which connects the switches Qv and Qu and ifjunctors of the superjunctor SJv are free simultaneously at one of theallowed time slots which will be called t'y, last it is determined ifthe free junctor at the time slot l'y is also free at the time slot t'x.

This program P18 is the continuation of the program P16 (or P17) whichhas enabled to determine the free link L at the time slot tx; with thiscode of free link, the computer, which is assumed to know theinterconnection between the two stages, determines the switch Qv towhich this free link is connected. For the program P18, the dataprocessing machine supplies then the following information:

the code of the switch Qv to which is connected the free link determinedby the program P16 (or P17), i.e. the code of the superjunctor SJv,

the code of the program P18,

the code of the input E'w to which channels are connected,

the allowed outgoing the code of the switch Qu to which is connected theinput the code of the link L'uv of the switch Q'u which is con nected tothe switch Qv, this code is determined by the data processing machinefrom the interconnection diagram between the two stages. ln the casewhere there are several links L'uv connecting the switches '14 and Qv,it is clear that the data processing machine will supply the codes ofthe said links Luv, each one of the said codes being used in turn if thesearch is not successful.

the code of mask of the allowed junctors,

the code of mask of the allowed outgoing channels,

the code of the trunk to which belong the allowed outgoing channels,

the time code Clx during which the link, determined by the program P16(or P17), is free,

the code 0000 in the flip-flops to 8 of the register Rgl,

the code of the phase Pcl of the sequential.

At each synchronous time slot, the code 0000 is compared to the spacecode read at this time in the memory M88 and at each asynchronous timeslot the said code is compared to the space code read at the precedingsynchronous time slot in the memory MSA. The results of thesecomparisons, corresponding to the memories M88 and MSA associated to theswitch Qv, are transferred in the register R1 (FIG. 9); they are takeninto account only at the time slot t'x, i.e. during the presence of thesignal lDr applied to the AND circuits SE11. The information of freejunctors at the time slot I): is stored in the register R38. If one ofthe junctors is free, in which case the 0R circuit 7 supplies a signalof opening of the AND circuits SE10, one shifts to the following step ofthe search which consists in searching if, at each allowed time slot,one of the allowed outgoing channels, the link L'uv and junctors of thesuperjunctor SJv are free simultaneously. During this step, the registerRM receives the results of the comparisons between the code 0000 and thespace codes of the memories M58 and MSA associated to the switch Q'u;this information of free links is compared, in the AND circuits SE8, tothe code 1 among l5 identifying the link L'uv which connects the switchQ'u, to which are connected the allowed outgoing channels, to the switchQv, to which is connected the free link determined by P16 (or P17); ifthe identity exists, the OR circuit 9 supplies an opening signal of theAND circuits SE10.

The register RG receives, during the program P18, the information offree channels, a channel being considered as free ii the expectedsignalling state corresponds to free state (condition SLSZ for the oddjunctions, FIG. 5) and ifthe trunk is not in alarm condition (conditionDrl for the odd trunks, FIG. 5).

When the allowed trunk is odd, it is sufficient to take into accountonly the information coming from the odd trunks; in the same way, whenthe allowed trunk is even, it is sufficient to consider only informationcoming from even trunks. This choice is carried out by means of the lesssignificant digit of the code of the trunk allowed, the said digit beingstaticized in the flip-flop 27 of the registers Rg3-Rg4 (FIG. 8). Thestate signal PAR of this flip-flop is equal to 0 if the allowed trunk isodd and equal to I if the allowed trunk is even.

As a result of the use of flip-flops for storing the alarm signals (FIG.5), the signal of free channel appears during a base time slot since itis possible to set up the half-link either during a synchronous timeslot, or during an asynchronous time slot (case of each group connectedto two inlets of a switch); the choice between these two solutionssynchronous or asynchronous for the time slot (y is directed by the timeslot r'x; thus, if I): is synchronous, ty will be asynchronous andreversely. This choice is obtained by applying to the comparator Cpl(FIG. 8) the complement to the less significant digit A'8 of the codeCr'x instead of the signal PAR. The information of free channels iscompared through the AND circuits SE3, to the code 1 among l5 (signalEw), identifying the input E'w to which the allowed outgoing channelsare connected. If there is indentity, the OR circuit 8 supplies theopening signal of the AND circuits SE10. lf at an allowed time slot ry(signal lD'r), the link L'uv is free and if it exists a free outgoingchannel, the contents of the register R] is transferred to the registerR36.

if it exists one or several free junctors, the third step consists thento search a junctor which is at the same time free in r; and in t'y. Forthat purpose, the contents of the registers R36 and R38 as well as themask Ml to M15 of the allowed junctors are compared through AND circuitsSE5. The choice of one of the junctors is performed in the same manneras during the other programs. If it exists a free path, the time code isgiven by the register Rg7.

In order to limit the search time, the signal De (FIG. 10) is elaboratedwhen the code Cr'x appears for the first time (conditionP18+P19).lDr.Pc1, FIG. 10) and the signal F1 is elaborated when the codeCt'x appears for the second time (condition P1B+Pl9).lDr.Pc1.De), whichmeans that all the possible cases have been scanned, including the casewhere the time t'y which is searched correspond to the same base timeslot as the time slot t'x given.

Program P19 The aim of program P19 is to identify the junctor and thetime slot t'y used for connecting at the time slot t): a link with anoutgoing channel; this program follows normally the program P16 (orP17). The information which are supplied by the data processing machineare the following:

the code of the switch Qv to which is connected the link identified bythe program P16 (or P17),

the code of the program P19,

the code of the mask of the allowed junctors,

the time code Ctx during which the link, determined by the program P16(or P17) is busy,

the code CE of the input E of the switch Qv to which is connected thelink identified by the program P16 (or P17); this code is staticized inthe flip-flops 5 to 8 of the register Rgl,

the code of the phase P0] of the sequential.

At each synchronous and asynchronous time slot, the code CE of the inputE of the switch Qv is compared respectively to the space codes of thememories M58 and MSA of the super junctor SJv; however the signalresulting from a comparison is taken into account only at the time slott'x (condition Pl9.De.lD, FIG. 7). if at the time slot t'x (conditionPUEJD, FIG. 7) there is identity between the two codes and if aconversation is in course (signal CV, FIG. 7), on the one hand, a digit0 is staticized in the register RJ and, on the other hand, a digit 1 isstored in the location Ml of the speech memory of the junctor and in theline selected at this time slot in the said memory. On the contrary, ifthere is identity but not conversation, on the one hand, a digit l isstaticized in the register RJ and a digit 0 is stored in the location M1of the memory MDJ. The digit 1 which appears at the time slot !'x in theregister RJ means that the half-link is not a conversation half-link andthe program P19 is over. As it has been explained in relation with FIG.7, if a conversation half-link is involved and if the time slot 1'): issynchronous, the digit M'1=l will be read at the asynchronous time slot1 Ay which is the searched time slot; reversely, if the time slot I): isasynchronous, the digit M'1=l will be read at the synchronous time slotlSy. As soon as the digit Ml==1 is written in the register R], thesignal VA appears and the time code ry searched is displayed in theregister R37. The register R39 gives thereafter the identity of thejunctor in the superjunctor SJv which has supplied the digit M'] l, i.e.the junctor used for the connection.

The scanning time of the digit M1 in the junctors is limited to the timeinterval between two clock time slots r'x; this time interval isdetected by the conditions De=P18+Pl9).lDr.Pcl and FF(P18+P19).IDT.P1.D.In order that the signal M1 may appear only once in the course of theprogram, it appears only for the condition PUIYeJD.

For reasons of safety of operation of the control exchange, provision ismade for using two scanning and searching circuits which will be calledA and B, each circuit A or B comprising the circuits of FIGS. 8, 9, 10and 11, the circuits as sociated to all the signalling memories anexample of achievement of which is shown on FIG. 5, the logical circuitsassociated to the output of all the comparators Cp and Cp, the circuitssending the space codes to all the comparators examples of achievementfor a superjunctor of which are shown on FIGS. l2 and 13.

If the circuit sending the space codes is the one of FIG. l2, the saidcircuit enabling to send the space code to all the comparators Cp and Cpof a superjunctor defined by the signal SGu or SGv supplied by thedecoders D03 and BM of FIG. 8, the possible ways of operation of thecircuits A and B are the following ones:

1. The circuits A and B may operate each one on turn;

2. The circuits A and B may put into operation simultaneously the sameprograms or different programs which concern the processing ofinformation coming from supergroups, i.e. the programs P and P24, andthis in a same supergroup, or in different supergroups. They may alsoput into operation simultaneously the programs P16 (or P17) and P18concerning a path search since the space codes which are sent are alwaysconstituted by zeros. On the contrary, they cannot put into operationsimultaneously the programs P16 (or P17) and P19 concerning a pathidentification only in different superjunctors since the space codeswhich are sent are in general different.

If the circuit sending the space codes is the one of FIG. 13, the saidcircuit enabling to send the space codes CE to the comparators Cp andthe space codes CE to the comparators Cp, the circuits A and B may thenput into operation simultaneously the programs P16 (or P17) and P19concerning a path identification in a same superjunctor.

if, instead of having circuits A and B having common comparators, eachcircuit A and B comprises the comparators C'p and Cp, the said circuitsA and B are then independent and a program P16 (or P17) and a programP19 may be put into operation simultaneously in the two circuits A andB.

While the principles of the present invention have been described inconnection with specific embodiments and particular modificationsthereof it is to be clearly understood that this description is made byway of example and not as a limitation of the scope of the invention.

We claim:

1. A time division multiplex data switching central exchange operatingin pulse code modulation in which the operations are controlled by adata processing machine; the said switching central exchange comprisinga switching network; circuits for a group ofp-trunks, where p is thenumber of digits of each channel message, connected to the inlet of theswitching network and provided for carrying out on reception aseries-parallel conversion and, on transmission, a parallel-seriesconversion of the digits of the messages of channels of ptrunks;circuits of detection and interpretation of the signalling digitsassociated with each circuit of a group of ptrunks comprising mainly asignalling memory in which are stored for each channel of the group thestate of the expected signalling and the indication of the change, ifany, of the signalling state with respect to the expected state; junctordata memories connected to the outlet of the switching network; eachjunctor comprising, in addition to a data memory, a time path memory andspace path memories for setting up a connection between two channels;the said memories being updated by the data processing machine inrelation with communications in course; a clock circuit provided forsupplying cyclic signals; said scanning and path search devicecontrolled by the data processing machine for processing the signalssupplied by circuits associated with the circuits of group of trunks,with the signalling memories and with the space path memories; saidscanning and path search device detecting the alarm signals from thetrunks, the new calls and the other changes ofstate of the signalling aswell as the search for a free path and the identification of busyconnections.

2. A data switching central exchange according to claim 1 in which thescanning and path search device is characterized by the fact that ineach circuit ofa group the alarm signals of the trunks appear at eachdigit time slot during which is processed a channel belonging to thesaid trunk; by the fact that the signalling memories are read in acyclic way and the signals read are applied to logical circuits whichdetect for each channel of a group the new calls and the other changesof state of the signalling; by the fact that the space path memories areread in a cyclic way and the space codes read are applied to acomparator which receives on the other hand the space code supplied bythe data processing machine, the said space code identifying across-point of the switching network in the case of an identification ofa busy connection or which does not correspond to any cross point at allin the case of a search of a free path; by the fact that circuits areprovided for storing and decoding the information necessary for theoperation of the scanning and search path device, the said informationbeing supplied by the data processing machine; by the fact that thesignals supplied by circuits of group are connected to a same switch; bythe fact that logical circuits associated with the signalling memoriescorresponding to the circuits of a group connected to a same switch; andby the fact that comparators associated with the space path memories ofthe junctors connected to a same switch are applied to a sequentiallogical circuit which determines the time and space coordinates of thetrunk in alarm or of the calling channel, or of the channel whichchanges its state without being calling or of the free path or of thebusy connection to be identified.

3. A data switching central exchange according to claim 1 in which thecodes of masks are supplied by the data processing machine; the saidcodes of masks enabling, in the sequential logical circuit, to take intoaccount only the alarm signals coming from certain circuits of groups oftrunks of a supergroup or the signals of changes of state coming fromlogical circuits associated to certain signalling memories of asupergroup, or the identity signals coming from comparators associatedto certain space path memories of a superjunctor or the signalsconcerning certain channels.

4. A data switching central exchange according to claim 1, in which thesequential logical circuit is characterized by the fact that theduration of a scanning concerning the alarms, or the new calls or thechanges of state other than the new calls as well as the duration of asearch for a free path or the identification of a busy link is limited.

5. A data switching central exchange according to claim I, in which theswitching network comprises two stages characterized by the fact thatthe search of a free path between two calling channels at the time slot1'): and one of the allowed outgoing channels at the time slots t'ydefined by a code of mask is carried out in two parts; the first partconsisting in searching a free link between the two stages of theswitching network at a time slot r'x, the second part consisting insearching a free junctor at a time slot tx and at one of the time slots!y as well as a free link and a free outgoing channel at a time slot r'yduring which the junctor, which is free at the time slot !'x, is alsofree.

6. A data switching central exchange according to claim I, in which theswitching network comprises two stages charac terized by the fact thatthe identification of the path used for a connection with an incomingchannel at the time slot r'x is carried out into two parts, the firstpart consisting in identifying link used at the time slot r'x and thesecond part consisting in identifying the junctor used as well as thetime slot !'y of the outgoing channel.

1. A time division multiplex data switching central exchange operatingin pulse code modulation in which the operations are controlled by adata processing machine; the said switching central exchange comprisinga switching network; circuits for a group of p-trunks, where p is thenumber of digits of each channel message, connected to the inlet of theswitching network and provided for carrying out on reception aseries-parallel conversion and, on transmission, a parallel-seriesconversion of the digits of the messages of channels of p-trunks;circuits of detection and interpretation of the signalling digitsassociated with each circuit of a group of p-trunks comprising mainly asignalling memory in which are stored for each channel of the group thestate of the expected signalling and the indication of the change, ifany, of the signalling state with respect to the expected state; junctordata memories connected to the outlet of the switching network; eachjunctor comprising, in addition to a data memory, a time path memory andspace path memories for setting up a connection between two channels;the said memories being up-dated by the data processing machine inrelation with communications in course; a clock circuit provided forsupplying cyclic signals; said scanning and path search devicecontrolled by the data processing machine for processing the signalssupplied by circuits associated with the circuits of group of trunks,with the signalling memories and with the space path memories; saidscanning and path search device detecting the alarm signals from thetrunks, the new calls and the other changes of state of the signallingas well as the search for a free path and the identification of busyconnections.
 2. A data switching central exchange according to claim 1in which the scanning and path search device is characterized by thefact that in each circuit of a group the alarm signals of the trunksappear at each digit time slot during which is processed a channelbelonging to the said trunk; by the fact that the signalling memoriesare read in a cyclic way and the signals read are applied to logicalcircuits which detect for each channel of a group the new calls and theother changes of state of the signalling; by the fact that the spacepath memories are read in a cyclic way and the space codes read areapplied to a comparator which receives on the other hand the space codesupplied by the data processing machine, the said space code identifyinga cross-point of the switching network in the case of an identificationof a busy connection or which does not correspond to any cross point atall in the case of a search of a free path; by the fact that circuitsare provided for storing and decoding the information necessary for theoperation of the scanning and search path device, the said informationbeing supplied by the data processing machine; by the fact that thesignals supplied by circuits of group are connected to a same switch; bythe fact that logical circuits associated with the signalling memoriescorresponding to the circuits of a group connected to a same switch; andby the fact that comparators associated with the space path memories ofthe junctors connected to a same switch are applied to a sequentiallogical circuit which determines the time and space coordinates of thetrunk in alarm or of the calling channel, or of the channel whichchanges its state without being calling or of the free path or of thebusy connection to be identified.
 3. A data switching central exchangeaccording to claim 1 in which the codes of masks are supplied by thedata processing machine; the said codes of masks enabling, in thesequential logical circuit, to take into account only the alarm signalscoming from certain circuits of groups of trunks of a supergroup or thesignals of changes of state coming from logical circuits associated tocertain signalling memories of a supergroup, or the identity signalscoming from comparators associated to certain space path memories of asuperjunctor or the signals concerning certain channels.
 4. A dataswitching central exchange according to claim 1, in which the sequentiallogical circuit is characterized by the fact that the duration of ascanning concerning the alarms, or the new calls or the changes of stateother than the new calls as well as the duration of a search for a freepath or the identification of a busy link is limited.
 5. A dataswitching central exchange according to claim 1, in which the switchingnetwork comprises two stages characterized by the fact that the searchof a free path between two calling channels at the time slot t''x andone of the allowed outgoing channels at the time slots t''y defined by acode of mask is carried out in two parts; the first part consisting insearching a free link between the two stages of the switching network ata time slot t''x, the second part consisting in searching a free junctorat a time slot t''x and at one of the time slots t''y as well as a freelink and a free outgoing channel at a time slot t''y during which thejunctor, which is free at the time slot t''x, is also free.
 6. A dataswitching central exchange according to claim 1, in which the switchingnetwork comprises two stages characterized by the fact that theidentification of the path used for a connection with an incomingchannel at the time slot t''x is carried out into two parts, the firstpart consisting in identifying link used at the time slot t''x and thesecond part consisting in identifying the junctor used as well as thetime slot t''y of the outgoing channel.